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M3488 september 2003 256 x 256 digital switching matrix this is advanced information on a new product now in development or undergoing evaluation. details are subject to change withou t notice. ? . 256 input and 256 output channel cmos digital switching matrix com- patible with m088 . building block designed for large capacity electronic exchanges, sub- systems and pabx . no extra pin needed for not-block- ing single stage and higher capacity synthesis blocks (512 or 1024 channels) . european telephone standard com- patible (32 serial channels per frame) . pcm inputs and outputs mutually compatible . actual input-output channel con- nections stored and modified via an on chip 8-bit parallel microproces- sor interface . typical bit rate : 2mbit/s . typical synchronization rate : 8khz (time frame is 125 m s) . 5v p0wer supply . cmos & ttl input/output levels com- patible . high density advanced 1.2 m m hcmos3 process main instructions controlled by the microproc- essor interface . channel connection/disconnection . output channel disconnection . insertion of a byte on a pcm output channel/disconnection . transfer to the microprocessor of a single pcm output channel sample . transfer to the microprocessor of a single output channel control word . transfer to the microprocessor of a selected 0 channel pcm input data dip40 pqfp44 ordering numbers: M3488b1 M3488q1 absolute maximum ratings symbol parameter test conditions unit v cc supply voltage -0.3 to 7 v v i input voltage -0.3 to v cc +0.3 v v o off state output voltage -0.3 to v cc +0.3 v i o current at digital outputs 30 ma p tot total package power dissipation 1.5 w t stg storage temperature range -65 to 150 c t op operating temperature range 0 to 70 c stresses above those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operating co n- ditions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de vice reliability. 1/18
pqfp44 pin connections (top views) dip40 exchange networks applications 256 pcm links network (160 or 192 dsm) : the 32 x 32 link module shown on the next page. 2048 pcm links network (1792 or 2048 dsm) : the 256 x 256 link network is shown above. 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 sync clock inp pcm7 v cc inp pcm0 n.c. d7 d6 d5 n.c. d4 d3 d2 d1 d0 dr n.c. out pcm7 rd v ss c/d a1 a2 s2 s1 n.c. wr cs1 reset cs2 d93tl040a 12 13 14 15 16 inp pcm6 inp pcm5 inp pcm4 inp pcm3 inp pcm2 inp pcm1 out pcm6 out pcm5 out pcm4 n.c. out pcm3 out pcm2 out pcm1 out pcm0 M3488 2/18
exchange networks applications (continued) single stage/sixteen devices configuration (32 by 32 links or 1024 channels). M3488 3/18
block diagram M3488 4/18
recommended operating conditions symbol parameter value unit v cc supply voltage 4.75 to 5.25 v v i input voltage 0 to 5.25 v v o off state input voltage 0 to 5.25 v clock freq. input clock frequency 4.096 mhz sync freq. input synchronization frequency 8 khz t op operating temperature 0 to 70 c capacitances (measurement freq. = 1mhz; t op = 0 to 70 c; unused pins tied to v ss ) symbol parameter pins (*) min. typ. max. unit c i input capacitance 6 to 15; 26 to 30; 32 to 36 5 pf c i/o i/o capacitance 20 to 24 15 pf c o output capacitance 1 to 4; 17 to 19; 25; 37 to 40 10 pf d.c. electrical characteristics (t amb = 0 to 70 c, v cc = 5v 5%) all d.c. characteristics are valid 250 m s after v cc and clock have been applied. symbol parameter pins (*) test condition min. typ. max. unit v ilc clock input low level 6 -0.3 0.8 v v ihc clock input high level 6 2.4 v cc v v il input low level 7 to 15 20 to 24 26 to 30 32 to 36 -0.3 0.8 v v ih input high level 7 to 15 20 to 24 26 to 30 32 to 36 2v cc v v oh output high voltage (level) 17 to 25 i oh = 5ma 2.4 v i oh output high current v oh = 2.4v 5 ma v ol output low voltage (level) 1 to 4 37 to 40 17 to 25 i ol = 5ma 0.4 v i ol output low current v ol = 0.4v 5 ma i il input leakage current 6 to 15 26 to 30 32 to 36 v in = 0 to v cc 5 m a i dl data bus leakage current 17 to 24 v in = 0 to v cc v cc applied; pins 35 and 36 tied to v cc , after device initialization 5 m a i cc supply current 16 clock freq. = 4.096mhz 15 30 ma (*) the pin number is referred to the dip40 version. M3488 5/18
a.c. electrical characteristics (t amb = 0 to 70 c, v cc = 5v 5%) all a.c. characteristics are valid 250 m s after v cc and clock have been applied. c l is the max. capacitive load. signal symbol parameter test condition min. typ. max. unit ck (clock) t ck t wl t wh t r t f clock period clock low level width clock high level width rise time fall time 230 100 100 244 25 25 ns ns ns ns ns sync (frame pulse) t sl t hl t sh t wh low level setup time low level hold time high level setup time high level width 60 30 80 t ck ns ns ns ns pcm input busses t s t h setup time hold time 5 +40 ns ns pcm output busses open drain t pd min t pd max propagation time referred to ck low level propagation time referred to ck high level c l = 150pf r l = 1k 45 110 110 140 ns ns reset t sl t hl t sh t wh low level setup time low level hold time high level setup time high level width 60 30 80 t ck ns ns ns ns wr, rd t wl t wh t rep t sh t hh t r t f low lvel width high level width repetition interval between active pulses high level setup time to active read strobe high level hold time from active write strobe rise time fall time t rep 40 + 2 t ck + t wl(ck) + + t r(ck) 100 t ck see formula 0 15 60 60 ns ns ns ns ns ns ns M3488 6/18
a.c. electrical characteristics (continued) signal symbol parameter test condition min. typ. max. unit cs1, cs2 t sl(cs-wr) t hl(cs-wr) t sh(cs-wr) t hh(cs-wr) t sl(cs-rd) t hl(cs-rd) t sh(cs-rd) t hh(cs-rd) low level setup time to wr falling edge low level hold time from wr rising edge high level setup time to wr falling edge high level hold time from wr rising edge low level setup time to rd falling edge low level hold time from rd rising edge high level setup time rd falling edge high level hold time from rd active case active case inactive case inactive case active case active case inactive case inactive case 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns c/ dt s(c/d-wr) t h(c/d-wr) t s(c/d)-rd) t h(c/d-rd) setup time to write strobe end hold time from write strobe end setup time to read strobe start hold time from read strobe end 130 15 20 20 ns ns ns ns a1, s1, a2, s2 (match in- puts) t s(match-wr) t h(match-wr) t s(match-rd) t h(match-rd) setup time to write strobe end hold time from strobe end setup time to read strobe start hold time from read strobe end 130 15 20 20 ns ns ns ns dr (data ready) t w t pd low state width dr output delay from write strobe end (active command) instructions 5 and 6 instruction 5, c l = 150pf 4.t ck 2.t ck 7.t ck ns ns d0 to d7 (interface bus) t s(bus-wr) t h(bus-wr) t pd(bus) t hz(bus) input setup time to write strobe end input hold time from write strobe end propagation time from (active) falling edge of read strobe propagation time from (active) rising edge of read strobe to high impedance state c l = 200pf c l = 200pf 130 15 120 80 ns ns ns ns a.c. testing, output waveform a.c. testing inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0", timing measurement are made at 2.0v for a logic "1"and 0.8v for a logic "0". M3488 7/18
pcm timing, reset, sync write operation timing M3488 8/18
read operation timing general description the M3488 is intended for large telephone switching systems, mainly central exchanges, digital line con- centrators and private branch exchanges where a distributed microcomputer control approach is ex- tensively used. it consists of a speech memory (sm), a control memory (cm), a serial/parallel and a parallel/serial converter, an internal parallel bus, an interface (8 data lines, 11 control signals) and dedicated control logic. by means of repeated clock division two timebases are generated. these are preset from an external synchronization signal to two specific count num- bers so that sequential scanning of the bases give synchronous addresses to the memories and i/o channel controls. different preset count numbers are needed because of processing delays and data path direction. the timebase for the input chan- nels is delayed and the timebase for output chan- nels is advanced with respect to the actual time. each serial pcm input channel is converted to par- allel data and stored in the speech memory at the beginning of any new time slot (according to first timebase) in the location determined by input pin number and time slot number. the control memory cm maintains the correspondences between input and output channels. more exactly, for any output pin/output channel combination the control memory gives either the full address of the speech memory location involved in the pcm transfer or an 8-bit word to be supplied to the parallel/serial output con- verter. a 9 th bit at each cm location defines the data source for output links, low for sm, high for cm. the late timebase is used to scan the output chan- nels and to determine the pins to be serviced within each channel ; enough idle cycles are left to the mi- croprocessor for asynchronous instruction process- ing. two 8-bit registers or1 and or2 supply feedback data for control or diagnostic purposes ; or1 comes from internal bus i.e. from memories, or2 gives an opcode copy and additional data to the microcom- puter. a four byte-five bit stack register and an in- struction register, under microcomputer control, store input data available at the interface. dedicated logic, under control of the microprocessor interface, extracts the 0 channel content of any se- lected pcm input bus, using spare cycles of sm. M3488 9/18
pins function symbol name pin assignement dip40 pqfp44 d7 to d0 data bus 17 to 24 13 to 21 c/ d input control 30 27 a1, s1, a2, s2 address select or match 26 to 29 23 to 26 cs1, cs2 chip select 33, 34 30, 31 wr data transfer enable 35 32 rd read enable 36 34 dr data ready 25 22 reset reset control 32 29 clock input master clock 6 1 sync input synchronization 7 2 in pcm 7 to 0 pcm input bus 8 to 15 3 to 10 out pcm 7 to 0 pcm output bus 37 to 40 and 1 to 4 35 to 38 and 40 to 43 M3488 10/18
pin description d7 to d0 data bus pins. the bidirectional bus is used to trans- fer data and instructions to/from the microprocessor. d0 is the least significant digit. the output bus is 8 bits wide ; input is only 5 bits wide. (d4 to d0) the bus is tristate and cannot be used while reset is held low. the meaning of input data, such as bus or channel numbers, and of expected output data is specified in detail by the instruction description. (pagg. 12-14) c/ d (pin 30) input control pin, select pin. in a write operation c/ d = 0 qualifies any bus content as data, while c/ d = 1 qualifies it as an opcode. in a read operation or1 is selected by c/ d = 0, or2 by c/ d = 1. a1, s1, a2, s2 address select or match pins. in a multi-chip con- figuration (e.g. a single stage matrix expansion), us- ing the same cs pins, the match condition (a1 = s1 and a2 = s2) leaves the command instruction as de- fined; on the contrary the mismatch condition modi- fies the execution as follows : instructions 1 and 3 are reversed to channel disconnection, instruction 5 is unaffected, instructions 2-4-6 are cancelled (not executed). bus reading takes place only on match condition, instruction flow is in any case affected. each pins couple is commutative : in a multichip con- figuration pins s1 and s2 give a hard-wired address selection for individual matrixes, while in single con- figuration s1 and a1 or s2 and a2 are normally tied together. cs1, cs2 commutative chip select pins. they enable the de- vice to perform valid read/write operations (active low). two pins allow row/column selection with dif- ferent types of microprocessors ; normally one is tied to ground. wr pin wr, when cs1 and cs2 are low, enables data transfer from microprocessor to the device. data or opcode and controls are latched on wr rising edge. because of internal clock resynchronization one sin- gle additional requirement is recommended in order to produce a simultaneous instruction execution in a multichip configuration : wr rising edge has to be 20 to 20 + t wl(ck) nsec late relative to clock falling edge. rd when cs1 and cs2 are low and match condition ex- ists, a low level on rd enables a register or1 or or2 read operation, through the bidirectional bus. in addition, the rising edge of rd latches c/ d and the match condition pins in order to direct the inter- nal flow of operations. because of internal clock resynchronization, one single additional require- ment is recommended in order to produce a simul- taneous instruction flow in a multichip configuration: the rd rising edge has to be 20 to 20 + t wl(ck) nsec late relative to clock falling edge. dr data ready. normally high, dr output pin goes low to tell the microprocessor that : a) the instruction code was found to be invalid ; b) executing instruction 5 an active output channel was found in the whole matrix array, that is a cm word not all "ones" was found in a configuration of devices sharing the same cs pins ; c) executing instruction 6 "0 channel extraction" took place and or2 was loaded with total number of messages inserted on 0 time slot. dr is active low about two clock cycles in case b and c ; in case a it is left low until a valid instruction code is supplied. reset reset control pin is normally used at the very be- ginning to initialize the device or the network. any logical status is reset and cm is set to all "ones" after reset going low. the internal initialization routine takes one time frame whatever the reset width on low level (mini- mum one cycle roughly), but it is repeated an integer number of time frames as long as reset is found low during 0 time slot. initialization pulls the interface bus immediately to a high impedance state. after the cm has been set to all "ones" the pcm output channels are also set to high impedance state. clock input master clock. typical frequency is 4.096mhz. first division gives an internal clock controlling the input and output channels bit rate. sync input synchronization signal is active low. typical frequency is 8khz. M3488 11/18
internal time bases are forced by synchronism to an assigned count number in order to restore channels and bit sequential addressing to a known state. count difference between the bases is 32, corre- sponding to two time slots, that is the minimum pcm propagation time, or latency time. inp pcm 7 to inp pcm 0 pcm input busses or pins ; they accept a standard 2mbit/s rate. bit 1 (sign bit) is the first of the serial sequence ; in a parallel conversion it is left adjusted as the most significant digit. out pcm 7 to out pcm 0 pcm output busses or pins ; bit rate and organiza- tion are the same as input pins. output buffers are open drain cmos . the device drives the output channels theoretically one bit time before they can be exploited as logical input channels (bit and slot compatibility is pre- served): this feature allows inputs and outputs to be tied together cancelling any analog delay of digital outputs up to t del max = t bit - t pd(pcm)max + t pd(pcm)min mixed rd and wr operations in principle rd and wr operations are allowed in any order within specification constraints. in practive, only one control pin is low at any given time when cs1 and cs2 are enabled. if by mistake or hardware failure both rd and wr pins are low, the interface bus is internally pushed to tristate condition as long as wr is held low and input registers are protected. registers or1 and or2 can be read in any order with a single rd strobe using c/ d as multiplexing control ; never the less this procedure is not recom- mended because the device is directed for instruc- tion flow only according to data latched by rd rising edge. multiple rd operations of the same kind are allowed without affecting the instruction flow : only "new" or1 or or2 read operations step the flow. input and output registers are held for sure in the previous state for the first 3 cycles following an op- code or an or2 read. functional description of specific microprocessor operations the device, under microprocessor control, performs the following instructions : 1 channel connection 2 channel disconnection 3 loading of a byte on a pcm output channel 4 transfer of a single pcm output channel sample 5 transfer of a single output channel control word 6 transfer of a selected 0 channel pcm input data according to an 8-bit mask previously stored in the "expected messages" register the instruction flow is as follows. any input protocol is started by the microprocessor interface loading the internal stack register with 2 bytes (4 bytes for instructions 1 and 3) qualified as data bytes by c/ d = 0 and a specific opcode quali- fied by c/ d = 1 (match condition is normally needed). after the code is loaded in the instruction register it is immediately checked to see whether it is ac- ceptable and if not it is rejected. if accepted the instruction is also processed as regards match con- dition and is appended for execution during the memories spare cycles. four cases are possible : a) the code is not valid ; execution cannot take place, the dr output pin is reset to indicate the error ; all registers are saved ; b) the code is valid for types 2, 4 and 6 but it is un- matched ; execution cannot take place, dr is not af- fected. c) the code is valid for types 1 and 3 and it is un- matched ; the instruction is interpreted as a channel disconnection. d) the code is valid and is either matched or of type 5 ; the instruction is processed as received. validation control takes only two cycles out of a total execution time of 4 to 7 cycles ; the last operation is updating of the content of registers or1 and or2, according to the following instruction tables. M3488 12/18
during a very long internal operation (device initiali- zation after reset going high or execution of in- struction 6) a new set of data bytes with a valid op- code is accepted while a wrong code is rejected. at the end of the current routine execution takes place in the same way as described before. at the end of an instruction it is normally recom- mended to read one or both registers. to exploit in- struction 6, however, it is mandatory to read register or2. this is because instruction 6, used between other short instructions of type 1 to 5, must have pri- ority and can be enabled only after the short instruc- tions have been completed. instruction 6 normally has a long process and a special flow which is de- scribed below. first a not-all-zero mask is stored in the "expected messages" register and in another "background" register. this operation starts the second phase of instruction 6 which is called "channel 0 extraction" and is repeated at the beginning of any new time frame. at the beginning of the time frame a new copy of activated channels to be extracted is made from the "background register" and put in the "expected messages" register. in addition the latter register is modified to indicate the exact number of messages that have arrived. the term messages covers any input 0 channel data with starting sequence different from the label 01. so using this label the number of expected messages can be reduced to correspond to the number of effective messages. if and only if the residual number is different from zero will the de- vice start the extraction protocol at the end of the current routine. the procedure is as follows : the dr output is pulsed low as a two cycle interrupt request and or2 is loaded with the total number of active channels to be extracted. the transfer of or2 content to the microprocessor continues the extraction which consists of repeated steps of or1 and or2 loading, indicating respec- tively the message and the incoming bus number. reading the registers in the order or1, or2 must be continued until completion or until the time frame runs out. with a new time frame a new extraction process be- gins, resuming the copy operation from the back- ground register. during extraction the active channels are scanned from the highest to the lowest number (from 7 to 0). while extraction is being carried out the time interval requirements between active rising edges of rd are minimum 4 to 7 t ck for sequence or2 - or1 and minimum 2 times t ck for sequence or1 - or2. more details are given in the following tables. instruction tables the most significant digits of or2 a7, a6, a5 are a copy of the pcm selected output bus ; the least sig- nificant digits of or2 are the opcode, c8 is the con- trol bit. in any case parentheses () define actual reg- ister content. instruction 1: channel connection control signals data bus notes match c/ d cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 x 0 0 0 1xxxxxbi2bi1bi01 st data byte: selected input bus. x 0 0 0 1 x x x ci4 ci3 ci2 ci1 ci0 2 nd data byte: selected input channel. x 0 0 0 1xxxxxbo2bo1bo03 rd data byte: selected output bus. x 0 0 0 1 x x x co4 co3 co2 co1 co0 4th data byte: selected output channel. yes/no1001xxxx0001in struction opcode yes 0 0 1 0 c7 (1 (bi2 c6 1 bi1 c5 1 bi0 c4 1 ci4 c3 1 ci3 c2 1 ci2 c1 1 ci1 c0 1) ci0) or1: cm content copy, that is, for mismatch condition, for match condition yes 1 0 1 0 a7 (bo2 (bo2 a6 bo1 bo1 a5 bo0 bo0 c8 1 0 0 0 0 0 0 0 0 0 0 1 1) 1) or2: that is, for mismatch condition for match condition M3488 13/18
instruction3: loading on a pcm output channel from a microprocessor byte control signals data bus notes match c/ d cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 x 0001 xxxxxci7ci6ci5 1 st data byte: most significant digits to be inserted. x 0001xxxci4ci3ci2ci1ci0 2 nd data byte: least significant digits to be inserted. x 0001 xxxxxbo2bo1bo03 rd data byte: selected output bus. x 0001xxxco4co3co2co1co04th data byte: selected output channel.. yes/no1001 xxxx 0100in struction opcode yes0010 c7 (1 (ci7 c6 1 ci6 c5 1 ci5 c4 1 ci4 c3 1 ci3 c2 1 ci2 c1 1 ci1 c0 1) ci0) or1: cm content copy, that is, for mismatch condition, for match condition yes1010 a7 (bo2 a6 bo1 a5 bo0 1 1 0 0 1 1 1 1 1 1) or2: that is. notes : s7...s0 is a parallel copy of a pcm data, s7 is the most significant digit and the first of the sequence. instruction2: output channel disconnection control signals data bus notes match c/ d cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 x 0 0 0 1xxxxxbo2bo1bo01 st data byte: selected output bus. x 0 0 0 1 x x x co4 co3 co2 co1 co0 2 nd data byte: selected output channel. yes 1 0 0 1 x x x x 0 0 1 0 instruction opcode yes001011111111 or1: cm content copy (output channel is inactive) yes1010 a7 (bo2 a6 bo1 a5 bo0 1 1 0 0 1 1 1 1 1 1) or2: that is. instruction4: transfer of a single pcm sample control signals data bus notes match c/ d cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 x 0 0 0 1xxxxxbo2bo1bo01 st data byte: selected output bus. x 0 0 0 1 x x x co4 co3 co2 co1 co0 2 nd data byte: selected output channel. yes 1 0 0 1 x x x x 1 0 1 1 instruction opcode yes0010 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 s1 c0 s0 or1: cm content copy if c8 = 1; or sm content sample if c8 = 0 yes1010 a7 (bo2 a6 bo1 a5 bo0 1 1 0 0 1 1 1 1 1 1) or2: that is. M3488 14/18
notes : 1. about mask bits mi0 to mi7 a logic "0" level means disabling condition, a logic "1" level means enabling condition. 2. a null mask or a reset pulse clear the mask and the deep background mask registers and disable channel 0 extraction function. 3. reading of or2 is optional after mask store or redefinition, because function is activated only by not-null mask writing. 4. after mask store (n2 n1 n0) is the sum of activated channels, after dr is the sum of active channels ; tn = 1/0 means activat ion/sup- pression of the function after store while after dr only tn = 1 can appear to tell a not-null configuration to be extracted. 5. reading of or2 is imperative after dr in order to step the data transfer ; reading of or1 is also needed to scan in descendin g order the priority register. relevant messages only are considered, that means only messages with a msd label different from 0 1. 6. (p2 p1 p0) is the pcm bus on which the message copied in or1 was found ; fn is a continuation bit telling respectively on lev el 1/0 for any more/no more extraction step to be performed. instruction5: transfer of an output channel control word control signals data bus notes match c/ d cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 x 0 0 0 1xxxxxbo2bo1bo01 st data byte: selected output bus. x 0 0 0 1 x x x co4 co3 co2 co1 co0 2 nd data byte: selected output channel. yes 1 0 0 1 x x x x 1 0 0 0 instruction opcode yes 0 0 1 0 c7 c6 c5 c4 c3 c2 c1 c0 or1: cm selected cm word copy. yes1010 a7 (bo2 a6 bo1 a5 bo0 c8 c8 1 1 0 0 0 0 0 0) or2: that is. instruction6: channel 0 selection mask store/data transfer control signals data bus notes match c/ d cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 x 0 0 0 1xxxxxmi7mi6mi5 1 st data byte: most sign. digits of selection mask. x 0 0 0 1 x x x mi4 mi3 mi2 mi1 mi0 2 nd data byte: least sign. digits of selection mask. yes 1 0 0 1 x x x x 1 1 1 0 instruction opcode mask store control yes 0 0 1 0 (previous content) or1: register is not affected. yes 1 0 1 0 n2 n1 n0 tn 1 1 1 0 or2: see below. first data transfer (after dr going low) yes 0 0 1 0 (previous content) or1: register is not affected. yes 1 0 1 0 n2 n1 n0 tn 1 1 1 0 or2: see below. repeated data transfer (after first or2 transfer) yes 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 or1: expected message stored in sm. yes 1 0 1 0 p2 p1 p0 fn 1 1 1 0 or2: see below. M3488 with less pcm links than 32 channels it is also possible to use M3488 when the pcm frames are made up of a number of channels other than 32. suppose that the pcm frames are made up of n- channels, which will be numbered from 0 to (n-1). each pcm frame will thus be made up of a number of bits multiplied by 8 ; this exactly equal to (n . 8). also, in this case, it is necessary to respect the tim- ing relationship between the different signals shown on the data sheet ; in particular, a relation-ship is al- ways carefully made between the rising edge of sync and the first clock (ck) bit contained in the slot time for bit 0 of channel 0. in order to use M3488 with these frames, it is suffi- cient, using the data bytes sent by the microproces- sor, to modify the numbering of a few channels. in particular : a) in all instructions in which reference is made to the input channel (n-1), the number 31 should be substituted for the number (n-1) ; b) in all instructions in which reference is made to the output channel 0, the number n should be sub- stituted for the number 0. M3488 15/18
pqfp44 (10 x 10) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e3 d3 e1 e d1 d e 1 k b pqfp44 l l1 0.10mm .004 dim. mm inch min. typ. max. min. typ. max. a 2.45 0.096 a1 0.25 0.010 a2 1.95 2.00 2.10 0.077 0.079 0.083 b 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 d 12.95 13.20 13.45 0.51 0.52 0.53 d1 9.90 10.00 10.10 0.390 0.394 0.398 d3 8.00 0.315 e 0.80 0.031 e 12.95 13.20 13.45 0.510 0.520 0.530 e1 9.90 10.00 10.10 0.390 0.394 0.398 e3 8.00 0.315 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k0 (min.), 7 (max.) outline and mechanical data M3488 16/18
dim. mm inch min typ max min typ max a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 52.58 2.070 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 48.26 1.900 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip40 outline and mechanical data M3488 17/18
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from i ts use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentione d in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmi- croelectronics products are not authorized for use as critical components in life support devices or systems without express wr itten approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia C belgium - brazil - canada - china C czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com M3488 18/18

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